JEDEC JESD8-6

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JEDEC JESD8-6 ADDENDUM No. 6 to JESD8 - HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS

standard by JEDEC Solid State Technology Association, 08/01/1995

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This standard is a 1.5 volt high performance CMOS-based interface document suitable for high I/O count CMOS and BiCMOS devices operating at frequencies in excess of 200 Mhz.

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Published: 08/01/1995 Number of Pages: 20File Size: 1 file , 410 KB